High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking laminated semiconductor chips vertically stacked and interconnecting the semiconductor chips using through-silicon vias (TSVs) have been introduced. Benefits of the 3D memory devices include a plurality of chips stacked with a large number of vertical vias between the plurality of chips and the memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of chips and a considerably smaller footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
The TSVs are through electrodes that penetrate a semiconductor chip including a semiconductor substrate typically composed of silicon. A parasitic capacitance is caused in each TSV when a signal through the semiconductor substrate, due to a ground potential of the semiconductor substrate surrounding the through electrode and poor isolation between the semiconductor substrate and the TSV. Furthermore, forming a stacked chip package including a large number (e.g., several tens to several hundreds) of semiconductor chips stacked on one another typically requires high precision of processing due to a length of the TSV (e.g., 30 μm to 50 μm) relative to a thickness of the semiconductor chip.